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Okay, now that we understand how to build
combinational logic gates using CMOS, let's

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turn our attention to the timing specifications
for the gates.

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Here's a simple circuit consisting of two
CMOS inverters connected in series, which

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we'll use to understand how to characterize
the timing of the inverter on the left.

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It will be helpful to build an electrical
model of what happens when we change V_IN,

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the voltage on the input to the left inverter.

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If V_IN makes a transition from a digital
0 to a digital 1, the PFET switch in the pullup

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turns off and the NFET switch in pulldown
turns on, connecting the output node of the

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left inverter to GROUND.

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The electrical model for this node includes
the distributed resistance and capacitance

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of the physical wire connecting the output
of the left inverter to the input of the right

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inverter.

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And there is also capacitance associated with
the gate terminals of the MOSFETs in the right

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inverter.

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When the output node is connected to GROUND,
the charge on this capacitance will flow towards

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the GROUND connection through the resistance
of the wire and the resistance of the conducting

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channel of the NFET pulldown switch.

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Eventually the voltage on the wire will reach
the potential of the GROUND connection, 0V.

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The process is much the same for falling transitions
on V_IN, which cause the output node to charge

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up to V_DD.

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Now let's look at the voltage waveforms as
a function of time.

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The top plot shows both a rising and, later,
a falling transition for V_IN.

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We see that the output waveform has the characteristic
exponential shape for the voltage of a capacitor

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being discharged or charged though a resistor.

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The exponential is characterized by its associated
R-C time constant, where, in this case, the

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R is the net resistance of the wire and MOSFET
channel, and the C is the net capacitance

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of the wire and MOSFET gate terminals.

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Since neither the input nor output transition
is instantaneous, we have some choices to

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make about how to measure the inverter's propagation
delay.

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Happily, we have just the guidance we need
from our signaling thresholds!

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The propagation delay of a combinational logic
gate is defined to be an upper bound on the

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delay from valid inputs to valid outputs.

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Valid input voltages are defined by the V_IL
and V_IH signaling thresholds, and valid output

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voltages are defined by the V_OL and V_OH
signaling thresholds.

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We've shown these thresholds on the waveform
plots.

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To measure the delay associated with the rising
transition on V_IN, first identify the time

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when the input becomes a valid digital 1,
i.e., the time at which V_IN crosses the V_IH

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threshold.

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Next identify the time when the output becomes
a valid digital 0, i.e., the time at which

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V_OUT crosses the V_OL threshold.

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The interval between these two time points
is the delay for this particular set of input

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and output transitions.

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We can go through the same process to measure
the delay associated with a falling input

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transition.

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First, identify the time at which V_IN cross
the V_IL threshold.

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Then find the time at which V_OUT crosses
the V_OH threshold.

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The resulting interval is the delay we wanted
to measure.

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Since the propagation delay, t_PD, is an upper
bound on the delay associated with *any* input

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transition, we'll choose a value for t_PD
that's greater than or equal to the measurements

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we just made.

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When a manufacturer selects the t_PD specification
for a gate, it must take into account manufacturing

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variations, the effects of different environmental
conditions such as temperature and power-supply

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voltage, and so on.

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It should choose a t_PD that will be an upper
bound on any delay measurements their customers

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might make on actual devices.

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From the designer's point of view, we can
rely on this upper bound for each component

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of a larger digital system and use it to calculate
the system's t_PD without having to repeat

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all the manufacturer's measurements.

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If our goal is to minimize the propagation
delay of our system, then we'll want to keep

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the capacitances and resistances as small
as possible.

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There's an interesting tension here: to make
the effective resistance of a MOSFET switch

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smaller, we would increase its width.

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But that would add additional capacitance
to the switch's gate terminal, slowing down

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transitions on the input node that connects
to the gate!

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It's a fun optimization problem to figure
out transistor sizing that minimizes the overall

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propagation delay.

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Although not strictly required by the static
discipline, it will be useful to define another

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timing specification, called the "contamination
delay".

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It measures how long a gate's previous output
value remains valid after the gate's inputs

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start to change and become invalid.

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Technically, the contamination delay will
be a lower bound on the delay from an invalid

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input to an invalid output.

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We'll make the delay measurements much as
we did for the propagation delay.

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On a rising input transition, the delay starts
when the input is no longer a valid digital

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0, i.e., when V_IN crosses the V_IL threshold.

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And the delay ends when the output becomes
invalid, i.e., when V_OUT crosses the V_OH

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threshold.

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We can make a similar delay measurement for
the falling input transition.

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Since the contamination delay, t_CD, is a
lower bound on the delay associated with *any*

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input transition, we'll choose a value for
t_CD that's less than or equal to the measurements

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we just made.

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Do we really need the contamination delay
specification?

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Usually not.

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And if not's specified, designers should assume
that the t_CD for a combinational device is

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0.

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In other words a conservative assumption is
that the outputs go invalid as soon as the

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inputs go invalid.

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By the way, manufacturers often use the term
"minimum propagation delay" to refer to a

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device's contamination delay.

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That terminology is a bit confusing, but now
you know what it is they're trying to tell

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you.

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So here's a quick summary of the timing specifications
for combinational logic.

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These specifications tell us how the timing
of changes in the output waveform (labeled

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B in this example) are related to the timing
of changes in the input waveform (labeled

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A).

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A combinational device may retain its previous
output value for some interval of time after

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an input transition.

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The contamination delay of the device is a
guarantee on the minimum size of that interval,

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i.e., t_CD is a lower bound on how long the
old output value stays valid.

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As stated in Note 2, a conservative assumption
is that the contamination delay of a device

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is 0, meaning the device's output may change
immediately after an input transition.

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So t_CD gives us information on when B will
start to change.

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Similarly, it would be good to know when B
is guaranteed to be done changing after an

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input transition.

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In other words, how long do we have to wait
for a change in the inputs to reflected in

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an updated value on the outputs?

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This is what t_PD tells us since it is a upper
bound on the time it takes for B to become

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valid and stable after an input transition.

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As Note 1 points out, in general there are
no guarantees on the behavior of the output

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in the interval after t_CD and before t_PD,
as measured from the input transition.

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It would legal for the B output to change
several times in that interval, or even have

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a non-digital voltage for any part of the
interval.

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As we'll see in the last video of this chapter,
we'll be able to offer more insights into

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B's behavior in this interval for a subclass
of combinational devices.

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But in general, a designer should make no
assumptions about B's value in the interval

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between t_CD and t_PD.

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How do we calculate the propagation and contamination
delays of a larger combinational circuit from

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the timing specifications of its components?

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Our example is a circuit of four NAND gates
where each NAND has a t_PD of 4 ns and t_CD

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of 1 ns.

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To find the propagation delay for the larger
circuit, we need to find the maximum delay

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from an input transition on nodes A, B, or
C to a valid and stable value on the output

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Y.

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To do this, consider each possible path from
one of the inputs to Y and compute the path

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delay by summing the t_PDs of the components
along the path.

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Choose the largest such path delay as the
t_PD of the overall circuit.

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In our example, the largest delay is a path
that includes three NAND gates, with a cumulative

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propagation delay of 12 ns.

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In other words, the output Y is guaranteed
be stable and valid within 12 ns of a transition

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on A, B, or C.
To find the contamination delay for the larger

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circuit, we again investigate all paths from
inputs to outputs, but this time we're looking

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for the shortest path from an invalid input
to an invalid output.

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So we sum the t_CDs of the components along
each path and choose the smallest such path

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delay as the t_CD of the overall circuit.

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In our example, the smallest delay is a path
that includes two NAND gates with a cumulative

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contamination delay of 2 ns.

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In other words, the output Y will retain its
previous value for at least 2 ns after one

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of the inputs goes invalid.